Techniques for integration of multiple active components (e.g. multiple integrated circuits, also referred to as chips or dies) into a single integrated circuit device play a significant role in facilitating small size and high performance integrated devices of various types.
Conventionally, packaged active components are furnished and arranged horizontally on a printed circuit board (PCB). The PCB provides mechanical support as well as electrical connection to the packaged active components. PCBs are typically formed with a laminated polymer substrate which may comprise a multilayer wiring providing electrical interconnection to the active component carried thereby. Accordingly, such PCBs are generally not stable during temperature variations and may shrink/warp when undergoing temperature changes. This consequently limits the density of electrical interconnection which may be accommodated in the PCB and accordingly limits the number and density of active components which may be carried thereby as well as the complexity of such active components. Specifically, with PCB only low to medium density of electrical interconnections may be provided to the active components in with density of about 1/10 expressed as the ratio between the nominal diameter of the interconnection and the nominal distance between interconnections. Provision of smaller interconnection pitches (higher interconnection densities exceeding 1/5) is generally restricted with PCBs.
Directed to allow small size integration of complex active components, which may require higher densities of electrical connections, wafer level packaging (WLP) technologies, which utilize the component substrate as the package substrate in flip chip technology, as well as System in Package (SIP) technologies, which are aimed at integrating multiple components in a common package, are increasingly used. SIP technologies allow multiple active components (dies/chips) to be packaged together within the same package thus enabling closer integration of different of types of chips, which serve as different modules of an integrated circuit device, to reside in a common package. The multiple active components/chips may include different modules of an integrated circuit (IC) device, for example a combination of logic (processor chip) and data-storage (memory-chip) components, a combination of logic and signal amplification and/or transmission/reception components or/and other combinations of components.
In this regard, the term packaging refers to the final stage of semiconductor device fabrication in which one or more dies/chips, which represent the core of the electronic device, are encased in a support that prevents physical damage and corrosion and support the electrical contacts required to assemble the integrated circuit into a system on a PCB.
A SIP integrated device typically includes multiple active components (two or more semiconductor chips/dies) carried by a carrier structure (also referred to herein as an interposer structure). The carrier/interposer structure is used to provide mechanical support and electrical interconnect to the active components carried thereby. Electrical connections to the active components and therebetween are generally provided by vertical electrical vias to connect the component on the top of substrate to the bottom interface with PCB or horizontal layers of interconnections such as IO lines on the top surface of the substrate. In an SIP integrated device, devices utilizing WLP technologies with flip chip configurations, the electrical interconnections are in many cases provided by utilizing horizontal layers of inter-connections (i.e. redistribution-layers (RDLs) formed on one or both of the top and bottom surfaces of the carrier structure) as well as utilizing electric pathways made through the carrier structure between the top and bottom surfaces (also known as through-vias and referred to herein as vias).
For example, U.S. Patent publication No. 2009/0212420 captioned “integrated circuit device and method for fabricating same” discloses fabricating an integrated circuit device including providing a semiconductor substrate comprising a first surface and a second surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semi-conductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit device is described.
General Description
There is a need in the art for a packaging technique allowing packaging together of two or more components of mixed technologies in a manner suitable for operation under wide/extensive range of conditions and/or under extreme conditions. There is also a need for a System in Package technique (SIP) for packaging two or more components of different semiconductor technologies on a common interposer structure which may be a passive interposer used for mounting the components or an active interposer in which one or more of the components are fabricated (e.g. on a top or bottom surface thereof). Further there is a need in the art for a SIP technique allowing wafer level packaging of one or more of the mixed technology components on to the common interposer structure.
Some of the known SIP techniques utilize laminate or ceramic or metal frame as part of the carrier structure. Other SIP techniques utilize a silicon carrier substrate/carrier. The thermal extension of a silicon carrier matches that of the silicon based semiconductor chips, and thus such a silicon interposer may provide a mechanically stable surface for carrying the silicon based components.
However, conventional techniques provide poor results when considering packaging of two or more components of mixed semiconductor technologies. Specifically, utilizing conventional SIP techniques for WLP packaging of an active component of one semi-conductor technology to an interposer of other technology may result in cracking and/or warping of the resulting integrated electrical device (interposer and/or active components thereon) in cases where operation under extreme thermal conditions is sought. This is inter-alia because of a mismatch between the coefficient of thermal expansion of the substrate and that of the various active components of different technologies, and also due to lack of sufficient heat evacuation provided under extreme temperatures by conventional techniques. Accordingly, packaging two or more active components of different technologies utilizing conventional SIP techniques typically results in warping, cracking of the integrated device when operating under extreme temperature conditions ranging from −55° C. to 150° C., and/or also in loss of mechanical stability and electrical interconnection integrity, which may consequently lead to failure in the device's operation. Such problems of loss of mechanical stability and electrical interconnection integrity are even more severe in cases where WLP technologies are used for the packaging, which are associated with high density of electrical connections.
Some known techniques utilize a relatively thick silicon carrier (e.g. with thickness exceeding 350 microns) in order to improve mechanical stability. However, thick silicon carriers generally provide poor thermal conductance which is insufficient for operating certain active components at high temperature conditions and thus results in deficient heat evacuation and consequently in deteriorated performance of the active components. Also, in existing integrated electronic devices in which multiple components of mixed technologies are packaged by SIP, the SIP packaging includes a ceramic carrier/substrate (since only the ceramic substrate is known to be compatible for mounting mixed technology components). However the ceramic carrier also provides poor results in terms of power dissipation which is in many cases insufficient for operating the active components at high temperature conditions.
The packaging technology of the present invention solves the above described deficiencies as well as other deficiencies of conventional techniques by providing a packaging technique allowing SIP packaging of two or more components of mixed technologies (e.g. combination of active components of the following semiconductor technologies: Silicon (Si), Silicon-Germanium (SiGe), Silicon-Carbide (SiC), Gallium-Arsenide (GaAs) and Gallium-Nitride (GaN)) in a manner suitable for operation under extensive/extreme conditions. To this end, the technique of the present invention enables packaging together two or more components of different technologies while allowing their operation under a wide range of temperatures (e.g. between −55° C. and 125° C.) and/or extreme range of temperatures (i.e. −65° C. to 150° C.) as well as providing near hermetically sealed packaging which is suitable for operating under various/high humidity conditions (e.g. 85% humidity at a temperature of 85° C.). The invention may be used to package together relatively large active components (dies) which size may for example be in the order of 25×25 mm2 while enabling their operation and structural integrity in a wide/extreme temperature range.
Moreover, the packaging technique of the present invention may provide radio frequency (RF) compatibility for high frequency applications and may be used for packaging together one or more high frequency active components utilizing/providing signals from DC and up to 10 to 20 GHz. The packaging technique of the present invention may be used to provide to such active components impedance controlled electrical connections and/or electromagnetic shielding to thereby allow their operation with reduced losses (e.g. reduced insertion/return losses). This allows utilizing the technique of the present invention for packaging signal processing chips together with high frequency components such as signal-amplifier and/or signal-transmitter/receiver. In this connection, the packaging technique of the present invention also provides superior thermal behavior with low thermal resistance (e.g. at least in certain areas of the substrate/carrier) and thus provides high power dissipation which allows packaging high power components, such as amplifiers, which are associated with substantial heat emission.
Thus, according to a broad aspect of the present invention there is provided an integrated circuit device including two or more active components and an interposer structure carrying the two or more active components. At least one of the components is carried on a surface of the interposer structure and at least one metal cap is furnished on that surface, encapsulating at least one of the active components.
In this connection it should be understood that the phrases interposer structure carrying or components carried by interposer should be interpreted herein broadly in the meaning that the components are mounted/furnished on the interposer and/or implemented as a part of the interposer. For example, one or more of the components may be furnished/glued to a surface of the interposer and/or one or more of the components may be fabricated as an integral part of the interposer (e.g. formed utilizing a pattern on one or more surfaces of the interposer or within the bulk of the interposer). In this regard, an interposer structure with which one or more components are integrated (e.g. fabricated thereon) is referred to herein as an active interposer while an interposer in which no component is integrated (e.g. components are merely mounted thereon) is referred to herein as a passive interposer.
Thus according to some embodiments of the invention the interposer structure is configured as an active interposer in which at least one of the two or more active components is implemented as an active component integrated with said interposer structure. Alternatively according to some embodiments of the invention the interposer structure is a passive one with no active components fabricated thereon.
According to some embodiments of the present invention the two or more active components of the integrated circuit device include components of at least two different semiconductor technologies. The interposer structure is configured and operable for carrying the two or more active components and allowing their operation under extreme temperature conditions. For example the integrated circuit device may be configured for operation under extreme temperature conditions ranging between −65° C. to 150° C. The two or more active components of different technologies may include components of at least two of the following technologies: Si chip, SiGe chip, SiC chip, GaAs chip and GaN chip.
According to some embodiments of the present invention interposer structure includes an interposer substrate and an arrangement of spaced-apart conductive vias formed in the substrate and respectively electrically connected to electric connections of the two or more active components. The electric connections of the conductive vias with the two or more active components include at least one of the following: wire-bonding and flip-chip electrical connections.
According to some embodiments of the present invention the interposer structure comprises one or more Redistribution Layers (RDLs) furnished on at least a bottom surface of the interposer structure for providing wiring connections to the conductive vias of the interposer structure. In some cases the RDLs include two-phase RDLs (e.g. for large and small areas).
According to some embodiments of the present invention the interposer structure includes a silicon (Si) based interposer substrate with an arrangement of Copper (Cu) conductive vias formed therein. According to some embodiments at least one of the one or more parameters are selected such that the interposer structure is mechanically stable under an extreme range of temperature conditions thereby preventing cracking and warping of the interposer structure and the active components carried thereby. These selected parameters include one or more of the following or all of them: material of the interposer substrate, a thickness of the interposer substrate, material of the conductive vias, diameters of the conductive vias, pitches of the conductive vias and a fraction of a surface area of the interposer structure covered by the conductive vias (e.g. for different regions of the substrate, different such fractions may be selected in accordance with the type/technology of the active elements carried at such different regions). To this end, the selected parameters may be chosen to ensure mechanical stability of the integrated mechanical stability of the integrated circuit device under a wide/extreme range of temperatures, while also to carry/mount active components of sizes up to about 25×25 mm.
Specifically, according to some embodiments of the invention the conductive vias are configured to provide the interposer structure with a coefficient of thermal expansion (CTE) matching the CTEs of two or more elements associated with at least two different technologies (e.g. two different semi-conductor technologies). This thereby enables operation of the device and the two or more active components under extreme temperature conditions.
According to some embodiments of the present invention the metal cap is configured and operable for enforcing the structural integrity and mechanical stability of said interposer structure under various thermal conditions. Specifically certain properties of the at least one cap such as its material composition (e.g. copper or stainless-steel), its thickness and its shape (e.g. lateral and height dimensions and curvature) may be selected to provide the desired degree of mechanical stability. In some cases, the material composition of the cap is selected to be similar to the material composition of conductive vias formed in a substrate of the interposer structure.
According to some embodiments of the present invention the a bonding material used for furnishing one or more of the active components carried/mounted on the interposer structure is selected to have a sufficient degree of flexibility/elasticity. The sufficient degree of flexibility/elasticity provides for reducing stresses which may occur under different temperature conditions due to a difference in coefficients of thermal expansion between the active components and the interposer structure.
According to some embodiments of the present invention the interposer substrate includes or is formed by a material (e.g. material composition) having relatively high thermal conductivity thereby enabling heat evacuation from the active components mounted on the interposer structure. Additionally or alternatively the conductive vias, which are made in a substrate of the interposer structure, are formed from a material (e.g. material composition) having relatively high thermal conductivity thereby further improving heat evacuation from the active components mounted on the interposer structure. In this connection according to some embodiments some properties of the vias, such as the locations and/or lateral dimensions and/or shapes of at least some of the conductive vias, are selected in accordance with locations and characteristic sizes of at least some of features (e.g. pattern features) of one or more of the active components. Specifically the location, sizes and possibly shapes of one or more of the conductive vias may be selected to provide sufficient thermal coupling between these one or more conductive vias and heat emitting features/parts/regions of the active components. Particularly one or more of the vias may be arranged to be co-aligned with (e.g. located under) some heat emitting parts/features if the active components have a surface thermal interfacing such feature which are associated with substantial heat emission. This further improves heat evacuation and diffusion of heat from these features during their operation under extensive-range/extreme temperature conditions, thus allowing operation of the device in such conditions. It is noted that in some cases such heat emitting parts/features are associated with at least one active component which is configured as an amplifier component (e.g. signal amplifier).
According to some embodiments of the present invention the metal cap is configured to define a cavity. The shape/dimensions of the cavity are configured to provide a sufficient gap between at least one active component encapsulated by the cap and other dielectric materials which may be associated with the integrated circuit device. This provides that the electrical impedance of that active component, which is encapsulated by the cap, is substantially not affected by the other dielectric materials and thereby facilitates proper operation of the active component.
In this connection, such configuration of the cap/cavity is used according to some embodiments of the invention for at least some of the components which are adapted for high frequency operation (e.g. operation with high frequency signals). Such a high frequency component may therefore be encapsulated by the metal cap such that its operational characteristics, being at least one of insertion and transmission losses, are not impaired by other dielectric materials in its vicinity.
In addition, in order to further facilitate operation of the integrated circuit device of the invention with at least one high frequency active component, which is associated with high frequency input/output signals, a certain electrical connection between certain vias of the interposer structure and the high frequency component are configured as RF connections utilizing balanced RF lines. For example, according to various embodiments of the present invention certain vias, connected to high frequency components, are configured as coaxial lines. Also, the electrical connections between those vias and the components are configured as balanced transmission lines and may include an arrangement of one or more of the following transmission configurations/structures along the line: coaxial configuration, strip line configuration, micro-strip line configuration and lateral-strip line (e.g. co-planar strip/waveguide). Utilizing such configurations of the transmission lines may be used to provide the active components with RF connection for frequencies in the order of up to 20 GHz.
According to certain embodiments of the present invention, the integrated circuit device is configured as a near hermetically sealed device capable of withstanding a broad range of humidity conditions. This is achieved by configuring the metal cap and its attachment to the interposer structure to provide fine leak sealing resulting in near hermetically sealed packaging suitable for operation under various humidity conditions.
According to some embodiments, the cap includes a vent opening defined thereon. The vent prevents, or at least reduces, pressure build up in a cavity defined between the cap and the interposer structure under varying temperature conditions (e.g. the vent is aimed at preventing the occurrence of a so called “pop-corn” effect at high temperature operation of the device). To preserve a fine leak sealing in such embodiments, the vent is generally covered with a material (e.g. porous/polymer material) allowing for pressure release though the vent while preventing, or substantially reducing, the amount of humidity passing therethrough.
According to some embodiments of the invention, the integrated circuit device includes a mold layer covering the top surface of the interposer structure with the two or more active components and the at least one cap which encapsulates at least one of the components. The mold layer may for example include (or be formed of) one or more dielectric materials. The cap (e.g. formed of conductive/metal material) is configured to define a cavity that provides a sufficient gap between at least one active component encapsulated by the cap and the mold layer along a height axis of the cap (e.g. along an axis perpendicular to the interposer surface at which the active component is mounted). The dimensions of the cavity and the gap are selected/configured such that the operational characteristics of a high frequency active component encapsulated in the cap are not impaired by the presence of the mold layer. Specifically, the cavity and the gap are configured to reduce the effects of an impedance mismatch between the active component and the mold layer when the former produces high frequency signals.
As noted above, in some embodiments, the cap includes a vent opening defined thereon. In some case the mold layer is arranged to cover the vent opening, thereby providing a near hermetically sealed packaging suitable for operating under various humidity conditions.
According to another broad aspect of the present invention there is provided a method for manufacturing an integrated circuit device, the method including:                providing an interposer substrate;        implementing an arrangement of through conductive vias in the substrate interposer to generate an interposer structure including at least the interposer substrate and the vias; the arrangement of the vias is configured to provide electrical connections to at least two active components of different technologies which are to be carried by the interposer structure; and        providing at least one active component of the active components and mounting the at least one active component on the interposer structure;        encapsulating the at least one active component by furnishing at least one cap over a surface of the interposer structure at which the active component is mounted.        
According to some embodiments of the present invention the interposer substrate is configured to form a passive interposer structure. Alternatively, the interposer substrate is configured as an active interposer including one of the active components implemented thereon. In the latter case the method further includes fabricating at least one of said active components in a region of the interposer substrate.
According to some embodiments of the present invention the method also includes configuring the arrangement of the vias such as to provide at different regions of the interposer structure different coefficients of thermal expansion (CTEs) substantially matching those of the active components which are to be carried by the interposer structure at those regions. The active components utilize different semiconductor technologies and are accordingly associated with different CTEs. Alternatively or additionally, according to some embodiments of the present invention, the method also includes configuring the arrangement of the vias to ensure sufficient heat conductance for evacuating heat from one or more features of at least one active component, which is associated with substantial heat emission.
According to yet another broad aspect of the present invention there is provided a technique for applying a mold layer to an integrated structure (e.g. integrated electronic device). The method includes providing an integrated structure to be molded, applying a mold layer on at least some regions of integrated structure(s). This includes baking the integrated-structure with the mold layer applied thereto at a substantially steady baking temperature. Then, the integrated-structure with the mold layer is gradually cooled down while preserving a substantially homogeneous temperature throughout the integrated-structure. According to some embodiments the cool down rate is in the order of about 10° C./hour. In this regard, the rate of the gradual cool down may depend on the size of the wafer/integrated-structure. Larger wafers typically require slower cool down rates and thus longer cool down durations while larger wafers may be cooled down faster (e.g. with rates of 20° C./hour) without developing warpage or cracks. According to some embodiment of the present invention metal (e.g. copper) plate(s) are thermally coupled to the integrated structure with the mold layer to facilitate gradual and homogeneous cooling. Specifically, in some cases, one or more plates of high weight are placed on top of the integrated structure to apply pressure to the structure and thereby further eliminate/prevent warpage/cracking of the structure.
Thus, the present invention provides a System-in-Package (SIP) technique advantageously allowing integration of active components of different technologies in a manner allowing their operation under a wide/extreme range of temperature and humidity conditions. A more detailed description of the various embodiments of the present invention and its advantages is provided in the detailed description of embodiments below.